The price-performance leader is now back with a powerful set of new features - 3D Viewers and Editors, VHDL Editor with facility of automatic project creation from VHDL source and Converters (CUPL, JEDEC, XILINX), Model Generators from VHDL for Mixed Mode and EDSpice Simulators with facility of automatic creation of model/ library along with other features. Apart from the major attraction, completely integrated design concept with Automatic...
Price: USD $100.00;
File Size: 114866 KB;
Platform: Windows 2000, Windows 2003, Windows 98, Windows XP
FIR HDL Writer 0.9
FIR HDL Writer is an EDA tool which generates FIR filters in clear text Verilog which may be synthesized to FPGA's or ASIC's. Design options include multiple channels, coefficient sets, interpolation, decimation, and resource utilization specifications. The designs are fully synchronous and registered to provide maximum clock frequencies. Clock rates in excess of 300 MHz have been observed with Stratix II and Virtex IV devices (using Quartus...
Price: USD $0.00;